In reply to Anudeep J:
I could not get your unpacked array of interfaces to connect.
rtl_q(rtl_intf.phy r1[0:1]);
Obviously, it worked by connecting individual interfaces to the dust, with the dut port having as formal individual interfaces. I restricted the number to 2 for testing.
Why do you want to make an array of interfaces in the rtl model?
// I have a TB interface, DUT Module which uses DUT Interface.
// I want to connect DUT and TB. How can I Connect? Please find the below code
// RTL INTERFACE
interface rtl_intf(input clk);
logic a;
logic b;
logic [1:0] c;
logic d;
modport phy(output c, input a, input b);
endinterface
// DUT MODULE MODIFIED --- WORKED
module rtl(rtl_intf.phy r1_0, r1_1); // r1[0:1]);
endmodule
// Original rtl
/* The interface port 'r1' must be passed an actual interface.
module rtl_q(rtl_intf.phy r1[0:1]);
endmodule */
// TB INTERFACE
interface tb_intf(input clk);
logic w;
logic x;
logic [1:0] y;
logic z;
endinterface
// What is the best approach to create 8 instances of TB Interface and connect
// to DUT in top module and how to do it?
module top ();
logic clk;
tb_intf tb_intf0(clk), tb_intf1(clk);
rtl_intf rtl_intf0(clk), rtl_intf1(clk);
rtl rtl1 ( .r1_0(rtl_intf0), .r1_1(rtl_intf1) ); // modified rtl OK
// Original rtl
// // rtl_q rtlq1 ( .r1[0](rtl_int0), .r1[1](rtl_int1) ); // line 36 ERROR
// ** Error: qifc.sv(36): (vlog-2730) Undefined variable: 'r1'.
// ** Error: (vlog-13069) qifc.sv(36): near "[": syntax error, unexpected '[', expecting ')'.
// rtl_q rtlq1 ( {rtl_int0 , rtl_int1} ); // line 36 ERROR
endmodule
Thanks for the solution. I need 8 interfaces because that’s how the RTL is defined. RTL has its own interface instantiated 8 times to support 8 different ports. Iam trying to connect them at top level using the TB interface by creating 8 instances. I cannot split them into separate interfaces. I need to use them as unpacked array. Could you please tell me how to connect them when its an unpacked array?
KISS, Keep It Simple Stupid (no insult here, just a point)
It’s unusual to have as RTL ports unpacked arrays of interfaces.
It’s hard to visualize and debug.
A stab at a solution; looks complicated but maybe it will steer you into an approach.
// I have a TB interface, DUT Module which uses DUT Interface.
// I want to connect DUT and TB. How can I Connect? Please find the below code
// RTL INTERFACE
interface rtl_intf(input clk);
logic a;
logic b;
logic [1:0] c;
logic d;
modport phy(output c, input a, input b);
endinterface
interface rtl_intf2(input clk);
rtl_intf rtl_intf0(CLK);
rtl_intf rtl_intf1(CLK);
endinterface
// DUT MODULE
module rtl(rtl_intf2 r);
endmodule
// TB INTERFACE
interface tb_intf(input clk);
logic w;
logic x;
logic [1:0] y;
logic z;
endinterface
interface tb_intf2(input clk);
tb_intf tb_intf0(clk);
tb_intf tb_intf1(clk);
endinterface
// What is the best approach to create 8 instances of TB Interface and connect
// to DUT in top module and how to do it?
module top ();
logic clk;
tb_intf2 tb_intf2i(clk);
rtl_intf2 rtl_intf2i(clk);
rtl rtl1 ( .r(rtl_intf2i));
// HERE
// Need to make signal connections between
// TB interface and RTL interface
endmodule
KISS, Keep It Simple Stupid (no insult here, just a point)
It’s unusual to have as RTL ports unpacked arrays of interfaces.
It’s hard to visualize and debug.
I’ve got to disagree with Ben here. Pretty much as soon as one starts to use SystemVerilog Interfaces within RTL, one quickly needs arrays of interfaces. They just go hand in hand and are prevalent within our RTL designs.
Tool support for arrays of interfaces was sketchy early on, but well supported by tools today.
Not sure if this thread will help the OP - it discusses similar things: Your text to link here…
Ideally TB and RTL interface should be same. But the difference here is my TB interface has many Debug signals, so I want to have them separately and connect them. But this is creating lot of extra code in my top for connections. So I needed a best approach to avoid that excess code.