In reply to Anudeep J:
KISS, Keep It Simple Stupid (no insult here, just a point)
It’s unusual to have as RTL ports unpacked arrays of interfaces.
It’s hard to visualize and debug.
A stab at a solution; looks complicated but maybe it will steer you into an approach.
// I have a TB interface, DUT Module which uses DUT Interface.
// I want to connect DUT and TB. How can I Connect? Please find the below code
// RTL INTERFACE
interface rtl_intf(input clk);
logic a;
logic b;
logic [1:0] c;
logic d;
modport phy(output c, input a, input b);
endinterface
interface rtl_intf2(input clk);
rtl_intf rtl_intf0(CLK);
rtl_intf rtl_intf1(CLK);
endinterface
// DUT MODULE
module rtl(rtl_intf2 r);
endmodule
// TB INTERFACE
interface tb_intf(input clk);
logic w;
logic x;
logic [1:0] y;
logic z;
endinterface
interface tb_intf2(input clk);
tb_intf tb_intf0(clk);
tb_intf tb_intf1(clk);
endinterface
// What is the best approach to create 8 instances of TB Interface and connect
// to DUT in top module and how to do it?
module top ();
logic clk;
tb_intf2 tb_intf2i(clk);
rtl_intf2 rtl_intf2i(clk);
rtl rtl1 ( .r(rtl_intf2i));
// HERE
// Need to make signal connections between
// TB interface and RTL interface
endmodule
Ben SystemVerilog.us