You need to name the begin/end block of the generate-for loop. You iterate over the block name.
for(genvar in_if=0 ; in_if<18; in_if++)
begin : blockname
interface ddr_if ();
end
for(genvar slice=0 ;slice<18 ;slice++ )
begin
dddr_chip ddr4 (.interface(blockname[slice].ddr_if));
end
For a simple array of instance you can also do
systemverilog]interface ddr_if 0:17;
for(genvar slice=0 ;slice<18 ;slice++ )
begin
dddr_chip ddr4 (.interface(ddr_if[slice]));
end
Thanks dave .. It is solved.
I am facing another issue.
Error:
*E PCIONC expression connected to an 'inout' port must be collapsible..
Below i mentioned my interface file
``` verilog
interface DDR4_if #(parameter CONFIGURED_DQ_BITS = 8) ();
timeunit 1ps;
timeprecision 1ps;
import arch_package::*;
parameter CONFIGURED_DQS_BITS = (16 == CONFIGURED_DQ_BITS) ? 2 : 1;
parameter CONFIGURED_DM_BITS = (16 == CONFIGURED_DQ_BITS) ? 2 : 1;
logic[1:0] CK; // CK[0]==CK_c CK[1]==CK_t
logic ACT_n;
logic RAS_n_A16;
logic CAS_n_A15;
logic WE_n_A14;
logic ALERT_n;
logic PARITY;
logic RESET_n;
logic TEN;
logic CS_n;
logic CKE;
logic ODT;
logic[MAX_RANK_BITS-1:0] C;
logic[MAX_BANK_GROUP_BITS-1:0] BG;
logic[MAX_BANK_BITS-1:0] BA;
logic[13:0] ADDR;
logic ADDR_17;
wire[CONFIGURED_DM_BITS-1:0] DM_n;
wire[CONFIGURED_DQ_BITS-1:0] DQ;
wire[CONFIGURED_DQS_BITS-1:0] DQS_t;
wire[CONFIGURED_DQS_BITS-1:0] DQS_c;
logic ZQ;
logic PWR;
logic VREF_CA;
logic VREF_DQ;
endinterface
Is that error indicate wire declaration of dq,dm pinss.
I changed to logic for those pins also. Still i am facing the same error
You can pass an array of interface instances to a module, but there is no syntax that allows you to concatenate a group of generated instances into an array.
In reply to Ram _p:
You can pass an array of interface instances to a module, but there is no syntax that allows you to concatenate a group of generated instances into an array.
This is certainly a deficiency in the language. We solve this problem by creating a “interface feedthru” module. Almost every one of our interface definitions has an paired feedthru module.
i.e. for our AXI interfaces:
The good thing about these feedthru modules is they usually dont need to be parameterized (even though the underlying interface are parameterized). i.e. for the above axi_if the awaddr wire has a parameterized width.
We use this to attached a named interface to a specific index of an array of interfaces - i.e
It’d be ideal it the language had a way to do this generically, rather than us being required to create the feedthru module per interface. What’s really needed, at its core is a “interface alias” like feature (similar to net alias).
The difficulty with alias is that unlike wires, instances can be parameterized, and interface port connections can behave like parameterization. Creating arrays of differently parameterized instances is big problem.
Not sure I understand the trouble completely. An interface array must be an array of identical interfaces (the language gives no way to instantiate anything else). That’s a given and ok with me.
My thoughts were the “interface alias” wouldn’t “tie” together two independent interfaces - rather, I’d declare the array of (identically parameterized) interfaces. Then “interface alias” the second named interface.
So, parameter types of everything would explicitly match. Of course, I’m probably missing something (perhaps tool, under the covers) obvious.
Actually thinking more I think I see the problem. It would work as I described above. But getting the grammar correct such that a user couldn’t do the reverse i.e. generate “N” independent (possible unique) interfaces, and try and “interface alias” them into an interface array. Yeah this latter thing wouldn’t work, and would need to be somehow disallowed.