Multiple interface connections to multiple DUT

SystemVerilog
2

You need to name the begin/end block of the generate-for loop. You iterate over the block name.

for(genvar in_if=0 ; in_if<18; in_if++)
  begin : blockname
    interface ddr_if ();
  end

for(genvar slice=0 ;slice<18 ;slice++ )
  begin 
    dddr_chip  ddr4 (.interface(blockname[slice].ddr_if));
  end

For a simple array of instance you can also do

interface ddr_if [0:17]();

for(genvar slice=0 ;slice<18 ;slice++ )
  begin 
    dddr_chip  ddr4 (.interface(ddr_if[slice]));
  end