In reply to Anudeep J:
I could not get your unpacked array of interfaces to connect.
rtl_q(rtl_intf.phy r1[0:1]);
Obviously, it worked by connecting individual interfaces to the dust, with the dut port having as formal individual interfaces. I restricted the number to 2 for testing.
Why do you want to make an array of interfaces in the rtl model?
// I have a TB interface, DUT Module which uses DUT Interface.
// I want to connect DUT and TB. How can I Connect? Please find the below code
// RTL INTERFACE
interface rtl_intf(input clk);
logic a;
logic b;
logic [1:0] c;
logic d;
modport phy(output c, input a, input b);
endinterface
// DUT MODULE MODIFIED --- WORKED
module rtl(rtl_intf.phy r1_0, r1_1); // r1[0:1]);
endmodule
// Original rtl
/* The interface port 'r1' must be passed an actual interface.
module rtl_q(rtl_intf.phy r1[0:1]);
endmodule */
// TB INTERFACE
interface tb_intf(input clk);
logic w;
logic x;
logic [1:0] y;
logic z;
endinterface
// What is the best approach to create 8 instances of TB Interface and connect
// to DUT in top module and how to do it?
module top ();
logic clk;
tb_intf tb_intf0(clk), tb_intf1(clk);
rtl_intf rtl_intf0(clk), rtl_intf1(clk);
rtl rtl1 ( .r1_0(rtl_intf0), .r1_1(rtl_intf1) ); // modified rtl OK
// Original rtl
// // rtl_q rtlq1 ( .r1[0](rtl_int0), .r1[1](rtl_int1) ); // line 36 ERROR
// ** Error: qifc.sv(36): (vlog-2730) Undefined variable: 'r1'.
// ** Error: (vlog-13069) qifc.sv(36): near "[": syntax error, unexpected '[', expecting ')'.
// rtl_q rtlq1 ( {rtl_int0 , rtl_int1} ); // line 36 ERROR
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue - SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment - https://verificationacademy.com/forums/announcements/free-book-component-design-example-…-step-step-process-using-vhdl-uart-vehicle