Code to generate pulses at a given rate using constraint randomization

SystemVerilog
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1

Hi,

I am trying to write a code to generate pulses at a given rate. Say pulse generator has to generate pulses at 1G, 2G, 5G, 10G rates. I tried writing the code as shown below but it’s not working.

class pulse;
  rand bit [3:0] rate;
  constraint c1  {rate inside {1,2,5,10};}
endclass

module generator;
  initial begin
    pulse pul;
    pul = new();
    
    repeat(4) begin
      pul.randomize();
      $display("pul.rate = %0b", pul.rate);
    end
    
    function gen_pulse;
    forever begin
      # pul.rate pulse = ~pulse;
    end
    endfunction
  end
endmodule

Can anyone please help me with this question.

Thanks in advance,
-Sruthi.

2

In reply to sruthikrapa:
Please use code tags to make your code easier to read. I have added them for you.

When you say something is “not working”, please explain in more detail what you expect to happen, versus what is actually happening. On what signal did you expect to see a pulse and what would it look like?

3

In reply to dave_59:

Hi Dave,

Thank you for the response.

I am trying to generate the pulses within the rates of 1,2,5 and 10. I have written point wise how I tried to analyse the question and wrote the above code.

  1. function pulse_gen should generate the pulse at the rates specified
  2. class which will have the declaration of the rand variable rate and the constraint for rate
  3. module which should randomize the rate within the given values
  4. sending the result of randomization to the function pulse_gen which will generate the pulse

I didn’t have a specific signal as such, I want to generate the signal pulse which is more like a clock which has its positive level for less than 50% of the time period. Here I am trying to assign that clock period using the variable rate.

Just like #4 clk = ~clk
I want the # rate and would like to define the rate within some range or within some specific rates as mentioned in this question.

For the above code I have written, I am getting the following error.
Error-[SE] Syntax error
Following verilog source has syntax error :
“testbench.sv”, 21: token is ‘function’
function gen_pulse;
^
Thanks,
Sruthi.

4

In reply to sruthikrapa:

Hi Dave,

Just wanted to add the below information too.

From the syntax #4 clk = ~clk, 4 is known as for example 4ns from the `timescale function specified in verilog. The same way I want to randomize the #number with #rate and wanted the rate to be 1G, 2G, 5G and 10G and would like to know how to implement this in systemverilog along with constraint randomization.

Thanks,
Sruthi.

5

In reply to sruthikrapa:

Hi,

we cant include delays in function. Try using task.

Regards
Kranthi

6

In reply to kranthi445:
You can’t declare tasks or functions inside begin/end blocks, and you can’t perform logical operators on class handles.

7

class pulse
rand bit[3:0]rate;
bit clk;
constraint p_dist{ rate dist{[3:0]:/clk};}
always #5 clk = ~clk;

pulse p;

initial begin
p = new();
assert(p.randomise());
transmit(p);
end
endclass

I have tried distributing constraints using weighted distribution.

8

In reply to sruthikrapa:
firstly inside function endfunction what actually pulse is…? it is name of a class.
function does not support any timing related operations and it should be declared outside “initial begin” “end” block.

class pulse;
  rand bit [3:0] rate;
  constraint c1 {rate inside {1,2,5,10};}
endclass
 
module generator;
  pulse pul;
  bit clk = 1;
  initial begin
  pul = new();
 
    repeat(10) begin
      pul.randomize();
      $display($time,"pul.rate =", pul.rate);
      $display($time,"value of clock",clk);
      #(pul.rate) clk = ~clk;
    end
     

  end
  /*
  always @(put.rate)
  #(pul.rate) clk = ~clk;
  
  initial begin
  #100 $finish;
  end

  initial forever clk = #(pul.rate) ~clk;
  */
endmodule