Clock with 45% to 50% duty cycle

SystemVerilog
1

Hi ,
Could you please let me know how to generate clock with 45% to 50% duty cycle

Thanks

2

In reply to srbeeram:
Simple math: 45% to 50% duty cycle is not a 100%in the cycle.
You most likely mean 45% to 55% duty cycle.
SO the clock could remain at 0 for 45ps and at 1 for 55p (or multiple x10 of these values.

3

In reply to ben@SystemVerilog.us:

I think they meant having a random duty cycle between 45% and 50%. It wasn’t clear if this was a jitter bounds, or a one-time setup. Either way, this kind of calculation could be used.

real clock_period = 1ns; // 1GHz for example
real clock_low, clock_high;

initial forever begin
         clock_high = clock_period * $urandom_tange(50,45)/100.0;
         clock_low = clock_period - clock_high;
         #clock_low clock = 1;
         #clock_high clock = 0;
end
4

In reply to dave_59:
Thanks Dave. The topic of random delays was also addressed in many posts. Here’s one of them
https://verificationacademy.com/forums/systemverilog/assign-random-delay-existing-clock

5

In reply to ben@SystemVerilog.us:

Thanks Ben and Dave for providing the clarifications