Clock with 45% to 50% duty cycle

SystemVerilog
3

In reply to ben@SystemVerilog.us:

I think they meant having a random duty cycle between 45% and 50%. It wasn’t clear if this was a jitter bounds, or a one-time setup. Either way, this kind of calculation could be used.

real clock_period = 1ns; // 1GHz for example
real clock_low, clock_high;

initial forever begin
         clock_high = clock_period * $urandom_tange(50,45)/100.0;
         clock_low = clock_period - clock_high;
         #clock_low clock = 1;
         #clock_high clock = 0;
end