I have two top level parameters in my module WIDTH and HEIGHT.
The use case of this module is such that WIDTH should always be less than HEIGHT.
is it possible to write an system verilog assertion just to check if this condition is always satisfied? should I use concurrent assertions or immediate assertions? is this(using sva) the best way to do it?
In reply to svishnu:
I have two top level parameters in my module WIDTH and HEIGHT.
The use case of this module is such that WIDTH should always be less than HEIGHT.
is it possible to write an system verilog assertion just to check if this condition is always satisfied? should I use concurrent assertions or immediate assertions? is this(using sva) the best way to do it?
I would write something like the following since parameters are evaluated at elaboration time, and remain unchanged throughout the simulation.
module m #(WIDTH=3, HEIGHT=2) (input bit a);
initial
ap_wh: assert(WIDTH < HEIGHT);
endmodule
"testbench.sv", 5: m.ap_wh: started at 0ns failed at 0ns
Offending '(WIDTH < HEIGHT)'
https://www.edaplayground.com/x/42SK
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
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In reply to ben@SystemVerilog.us:
I would write an if outside of any initial block, since this is evaluated during elaboration and this can stop a compile in case of an error:
module some_module();
// ...
if (WIDTH >= HEIGHT)
$error($sformatf("Illegal values for parameters WIDTH (%0d) and HEIGHT (%0d)", WIDTH, HEIGHT));
endmodule
The if is actually a generate block, which will get elaborated only in case of a wrong parametrization. The standard allows $error(…) as elaboration severity messages (i.e.e outside of procedural code). You don’t actually need an assertion here, as you’re not checking any DUT behavior.