In reply to svishnu:
I have two top level parameters in my module WIDTH and HEIGHT.
The use case of this module is such that WIDTH should always be less than HEIGHT.
is it possible to write an system verilog assertion just to check if this condition is always satisfied? should I use concurrent assertions or immediate assertions? is this(using sva) the best way to do it?
I would write something like the following since parameters are evaluated at elaboration time, and remain unchanged throughout the simulation.
module m #(WIDTH=3, HEIGHT=2) (input bit a);
initial
ap_wh: assert(WIDTH < HEIGHT);
endmodule
"testbench.sv", 5: m.ap_wh: started at 0ns failed at 0ns
Offending '(WIDTH < HEIGHT)'
https://www.edaplayground.com/x/42SK
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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