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  • assertion to check valid |-> 8 clks rsp

assertion to check valid |-> 8 clks rsp

SystemVerilog 5107
#systemverilog #ASSERTION 73
UVM_SV_101
UVM_SV_101
Full Access
61 posts
February 19, 2021 at 8:20 am

Hi,

I trying to write assertion to check that if valid is high, rsp should be high only after 8 clks. Valid can be high on consecutive clks and hence rsp should be high on consecutive clks as well.

**My question is if we were to implement the logic to drive rsp, we would use fork-join and call automatic task since this is pipelined process. Does assertion take care of this if it does how does that work? Is there a new assertion triggered every-time valid==1 and separate memory is allocated to check that assertion?

clks 0 1 2 3 4 5 6 7 8 9 10
     v v             r r 

assert property p1;
 
property p1;
   @(posedge clk) (valid==1) |-> rsp==0[*7] ##1 rsp==1;
endproperty

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dave_59
dave_59
Forum Moderator
8757 posts
February 19, 2021 at 10:18 am

In reply to UVM_SV_101:

Yes, an assertion takes care of this by creating a new thread for every attempt, each with its own set of local variables and state information.

Your property will not work because rsp is not necessarily 0 for the 8 cycle duration. You would have to do

property p1;
   bit v;
   @(posedge clk) (1,v=valid) ##8 rsp==v;
endproperty

After 8 cycles, there would be 8 threads, each with their own local copy of v.

— Dave Rich, Verification Architect, Siemens EDA

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2038 posts
February 19, 2021 at 10:34 am

In reply to UVM_SV_101:

Your assertion is almost correct. Should be
 @(posedge clk) (valid==1) |=> rsp==0[*7] ##1 rsp==1;
At E every clocking event (the @(posedge clk) the property of the assertion is triggered independently from any other triggered assertions and has a life of its own.

I posted on LinkedIn An anecdote: is SVA a soap pipe?

At every blow event of a soap pipe, a bubble property is emitted. That bubble has a life of its own. It begins to spin, examining its initial states and composition, and then has several outcomes:

· It could disappear as if this bubble property was totally meaningless and vacuous.

· It could split and issue a new property bubble, and this process can repeat itself multiple times. Each of these new bubbles then has a life of its own.

. One or more of these split bubbles could be seen shining with glow and happiness as if it succeeded, or it can come down in a flash crashing miserably into failure.

Note: I describe this analogy to SVA assertions as a response to questions I see at the https://verificationacademy.com/forums/systemverilog where many users fail to understand the SVA inner model on how properties are handles starting from the clocking event.

Actually, to better understand the SVA model, I encourage you to read my paper Understanding the SVA Engine,

https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
...
1) SVA Package: Dynamic and range delays and repeats https://rb.gy/a89jlh
2) Free books: Component Design by Example https://rb.gy/9tcbhl
Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
3) Papers:
- Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment

dave_59
dave_59
Forum Moderator
8757 posts
February 19, 2021 at 11:27 am

In reply to ben@SystemVerilog.us:

Ben, your assertion does not take care of the overlapping responses.

— Dave Rich, Verification Architect, Siemens EDA

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2038 posts
February 19, 2021 at 11:41 am

In reply to dave_59:

Oops! You're correct, my error.
A simple sequence like the one you have shown is good.
Thanks,
Ben systemverilog.us

UVM_SV_101
UVM_SV_101
Full Access
61 posts
February 19, 2021 at 12:47 pm

In reply to dave_59:

Quote:
In reply to UVM_SV_101:

Yes, an assertion takes care of this by creating a new thread for every attempt, each with its own set of local variables and state information.

Your property will not work because rsp is not necessarily 0 for the 8 cycle duration. You would have to do

property p1;
   bit v;
   @(posedge clk) (1,v=valid) ##8 rsp==v;
endproperty

After 8 cycles, there would be 8 threads, each with their own local copy of v.


Hi Dave,

According to logic there would be new thread every posedge of clk? Wouldnt that affect the performance?

Is there a way to put condition on it?

EDIT::
Oh never mind, that assertion takes care of valid==0, rsp==0 as well.

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2038 posts
February 19, 2021 at 1:21 pm

In reply to UVM_SV_101:

See my last reply at
https://verificationacademy.com/forums/systemverilog/assertion-req-and-gnt-signals
Ben systemverilog.us

rag123
rag123
Full Access
148 posts
February 20, 2021 at 5:41 pm

In reply to ben@SystemVerilog.us:

Hi Ben/Dave,

I have a question on the above assertion. I simulated it and i see the assertion passes at 170ns.I see the first detection of valid =1 happens at 30ns and then after 8 clock cycles inclusive, i dont see the rsp becoming one after 8 cycles and i still see the assertion passed. Can you help me tell why the assertion passed at 170ns?

here is the code

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2038 posts
February 20, 2021 at 6:27 pm

In reply to rag123:
The assertion looks ok and it is a good solution.
The confusion may be in the way you read the waveforms. 

// stimulus 
@(posedge clk) #1;  
     if (!randomize(valid,rsp)
// valid is sampled in the Preponed region of @(posedge clk) 
// From the waveform you when you see valid gong to a 1'b1, it is after 1 ns 
// but regardless of that, the sampling of valid is zero not a one.

Ben SystemVerilog.us
ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2038 posts
February 20, 2021 at 6:55 pm

In reply to ben@SystemVerilog.us:

If you want vacuity when valid==0, you can use this definition of a property 

property_statement ::=
property_expr ;
  if ( expression_or_dist ) property_expr
  [ else property_expr ]
 
ap2: assert property( @(posedge clk) if(!valid) 0 |-> 1 // vacuity because of the 0 
                                         else  ##8  rsp);

Ben SystemVerilog.us
ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2038 posts
February 21, 2021 at 4:53 am

In reply to dave_59:

Quote:
In reply to ben@SystemVerilog.us:

Ben, your assertion does not take care of the overlapping responses.


This solution has no overlapping issue. .
@(posedge clk) (valid==1) |-> ##8 rsp==1;
BTW this is identical to the the property with the "if" clause
Ben systemverilog.us
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