In reply to UVM_SV_101:
Your assertion is almost correct. Should be
@(posedge clk) (valid==1) |=> rsp==0[*7] ##1 rsp==1;
At E every clocking event (the @(posedge clk) the property of the assertion is triggered independently from any other triggered assertions and has a life of its own.
I posted on LinkedIn An anecdote: is SVA a soap pipe?
At every blow event of a soap pipe, a bubble property is emitted. That bubble has a life of its own. It begins to spin, examining its initial states and composition, and then has several outcomes:
· It could disappear as if this bubble property was totally meaningless and vacuous.
· It could split and issue a new property bubble, and this process can repeat itself multiple times. Each of these new bubbles then has a life of its own.
. One or more of these split bubbles could be seen shining with glow and happiness as if it succeeded, or it can come down in a flash crashing miserably into failure.
Note: I describe this analogy to SVA assertions as a response to questions I see at the https://verificationacademy.com/forums/systemverilog where many users fail to understand the SVA inner model on how properties are handles starting from the clocking event.
Actually, to better understand the SVA model, I encourage you to read my paper Understanding the SVA Engine,
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
1) SVA Package: Dynamic and range delays and repeats https://rb.gy/a89jlh
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- Understanding the SVA Engine,
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