Assertion to check signal asserted for only one clock cycle

SystemVerilog
1

Hello,

Lets say I have a clk and single bit signal “valid”, Now I want to check whenever valid is asserted in any posedge of clock, then in the next consecutive posedge it should get de-asserted.

I tried,


 property sva_P1 
   @(posedge clk) $rose(valid)|=> $fell(valid);
 endproperty

This above code is executing perfectly; But there are are few corner cases where it is showing inappropriate behavior

  1. The assertion is Passing when valid is asserted at negedge of clock and deasserted at next negedge of clock. (It should Fail here)
  2. The assertion is not hitting when valid is asserted at posedge of clock and deasserted in next negedge of clock. (It should Fail here).

I want a assertion to check those above mention scenarios also; Is there any better way to rewrite this assertion.
Thank you
Dhruvesh.b

2

In reply to Dhruvesh.b:

The assertions are working as expected, your conclusions are wrong because you did not consider the sampling values at the clocking event.
See my comments

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3

In reply to ben@SystemVerilog.us:

Hi Ben, Thank you for sharing your understanding.


property sva_p2;
  @(posedge clk) $rose(signal) |-> @(negedge clk) $fell(signal);
endproperty

I tried this assertion “sva_p2” and it is working perfectly fine even with the cases mentioned above…
As our expectation, both cases are failing…

But now the question is that, Is the assertion “sva_p2” can be considered correct, As it is having posedge and negedge event of the same clock…

Waiting for your insight on the same,
Thank You,
Dhruvesh.B

4

In reply to Dhruvesh.b:

perhaps in addition to your sva_p1 property, you want valid to be stable during negedge?


``` verilog

property p1;
  @(negedge clk) $stable(valid);
endproperty
5

In reply to UVM_SV_101:

I want to check whenever valid is asserted in any posedge of clock, then in the next consecutive posedge it should get de-asserted.

The original assertion is correct. Assuming that Your RTL design is a synchronous system with one clock, there is NO reason to use a muticlock verification approach.


//I want to check whenever valid is asserted in any posedge of clock, 
/ then in the next consecutive posedge it should get de-asserted.
@(posedge clk) $rose(valid)|=> $fell(valid);

// ON the following suggestion 
 @(negedge clk) $stable(valid);
// I don't see a need.  Also, with no antecedent this will have failures. 
// Are you requiring that valid is always a single value forever? 
// That's what  @(negedge clk) $stable(valid); provides (except for the 1sr cycle single b=valid 0s set to its default or initialized value.

Ben SystemVerilog.us