UVM

UVM
53

In reply to Muthamizh:

They are starting from 0, but with undefined value (x). The data are synchronous with your clock.

54

In reply to chr_sue:

Is that correct? Cant i make it to start it from 0? nd why is it starting from x?

55

In reply to Muthamizh:

Yes, it is. You can’t see the seq_items in the waveforms. There you see only the signals/variables. Because you are using logic as data type you see the x. logic is initialized to x.

56

In reply to chr_sue:

Thanks for your help and suggestions. Im thinking about using $root to control reset from tb top itself. In that case, how the driver logic should be changed?

57

In reply to Muthamizh:

If you are replazing the logic data type by bit you’ll see the 0 instead of x. Another wa is to initialize your values to z. But what you have is completely fine.

58

In reply to chr_sue:

i have changed it to bit. Still it starts from x. Then it is not the correct one, right??

59

In reply to Muthamizh:

You have to do this in the interface definition.

60

In reply to chr_sue:

i did it in interface only.

61

In reply to Muthamizh:

I think you have seen in is 0 from the beginning and out and state is x. This comes from your design.Simple Verilog does not know 2-state variables. There is the type reg used.

62

In reply to chr_sue:

Yes in is 0 from the beginning. Thank you so much for your suggestions. They were very helpful and useful. Thanks again.

63

In reply to Muthamizh:

What is phase objection actually?

64

In reply to Muthamizh:
What do you mean with phase objection?

The objection mechanism is used stop the simulation after completing all sequences and run_phase tasks.
If you do not implement this mechanism the simulation stucks at time 0.
You can implement the objections in different objects (components, sequences).

65

In reply to chr_sue:

This is what i wanted to know. Thank you for the explanation.

66

In reply to Muthamizh:
Now i need to do another testcase for the same fsm. i need to stop the clock generation and check the response. How to do that? Any idea please?

67

In reply to Muthamizh:
how to disable clock generation in between, which is being generated from top module? Please help me out.

68

In reply to Muthamizh:

You can implement a signal (clock_dis signal) in your module interface, this signal can be driven by your uvm_driver. Use this signal to mask the clock signal in top/interface where your clock is generated.

UVM driver takes config/seq_item’s attribute to control clock_dis signal.

Please visit this thread, it may help you implement the idea:
https://verificationacademy.com/forums/uvm/clock-generator

You can try it while waiting for someone else to provide better solution.

69

In reply to chris_le:

Thank you so much for your suggestion.

70

In reply to Muthamizh:

There is no frequency specifications for my fsm rtl. So how to calculate the frequency with clock generated?

71

In reply to Muthamizh:

What is IP level verification? i searched for the abbrevation of IP. But I dint find it anywhere. Could you please explain IP level verification?

72

In reply to Muthamizh:

You have much learning to do. First start by improving your search skills:

http://lmgtfy.com/?q=IP+level+verification

First two hits explain Verification IP.