In reply to Muthamizh:
You can implement a signal (clock_dis signal) in your module interface, this signal can be driven by your uvm_driver. Use this signal to mask the clock signal in top/interface where your clock is generated.
UVM driver takes config/seq_item’s attribute to control clock_dis signal.
Please visit this thread, it may help you implement the idea:
https://verificationacademy.com/forums/uvm/clock-generator
You can try it while waiting for someone else to provide better solution.