VHDL module verification

UVM
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Hello Verification Academy,

I am verifying a module which is in VHDL for that I am using Makefile. And the command which I am using is

vcom -work $(work) $(RTL) $(SVTB1) $(SVTB)

After executing this command all VHDL files are getting compiled while in interface file I am getting syntax error as

  near "interface": syntax error can you tell me how to solve this error?
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In reply to truptis_135:

I guess you are trying to compile SV Code with the vcom command, because VHDL does not know the Keyword ‘interface’.
This is not legal. You have to compile SV Code with vlog -sv.
BTW this is a tool related question and the Forum is not for tool issues.

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In reply to chr_sue:

thank you sir I got the solution from your reply.