Thank you for response. Here is snippet of my code for memory model and example of write task.
Creating of memory_model:
// Default memory model.
class memory_model extends uvm_mem;
`uvm_object_utils(memory_model)
function new(string name = "memory_model");
super.new(name, // Name of the memory model
ROW_NUM, // The address range
WORD_WIDTH, // The width of the memory in bits
"RW", // Access - RW or RO
UVM_NO_COVERAGE); // Functional coverage
endfunction
endclass: memory_modelAfter that in my uvm_block class (extend uvm_reg_block) a have:
rand memory_model m_mem;
..
virtual function void build;
// First part of HDL path
add_hdl_path("top.dut.HDL");
// Memories
m_mem = memory_model::type_id::create("m_mem");
m_mem.configure(this, "");
m_mem.add_hdl_path_slice(.name("my_mem"), .offset(0), .size(WORD_WIDTH));And for use in sequence I am using for example this task for write word to memory:
task automatic write_word_to_memory(
input logic [WADD_W-1:0] wadd, // Word address in memory
input logic [DIN_W-1:0] data, // Data that will be written
input memory_model object_id // ID of object
);
uvm_status_e status;
uvm_reg_data_logic_t outgoing = data;
object_id.write(status, wadd, outgoing, UVM_BACKDOOR);
assert( status == UVM_IS_OK ) begin
`uvm_info("write_word_to_memory", $sformatf("Write to %s address %0d | data %8h", object_id.get_name(), wadd, data), UVM_MEDIUM);
end else begin
`uvm_error("write_word_to_memory", "Status of UVM_BACKDOOR approach is not OK!")
end
endtask: write_word_to_memoryCall in sequence:
mem_backdoor.write_word_to_memory(
read_address, // Word address in memory
'X, // Data that will be written
mem_backdoor.m_mem // ID of object
);