After more searching I think, that problem is not in my code, but it is the definition of task write and read in uvm_mem file in UVM package.
https://www.vmmcentral.org/uvm_vmm_ik/files3/reg/uvm_mem-svh.html#uvm_mem.write
As you can see, there is uvm_reg_data_t used for value, which is 2-state. And I would need there uvm_reg_data_logic_t type, which is 4-state.
virtual task write(output uvm_status_e status,
input uvm_reg_addr_t offset,
input uvm_reg_data_t value,
input uvm_path_e path = UVM_DEFAULT_PATH,
input uvm_reg_map map = null,
input uvm_sequence_base parent = null,
input int prior = -1,
input uvm_object extension = null,
input string fname = "",
input int lineno = 0
Is there some easy way how to change this without recreating my own tasks for write and read, please?