UVM objection raising mechanism

I understand we need to raise objection before starting sequence and ending it after body task is done. However this is based on understanding that we would be running just 1 sequence in 1 test. Say I have 2 sequence, transmit and reset sequence. I would start reset sequence with config_db method however I would run it in reset_phase as opposed to main_phase. I would start my transmit sequence in main_phase. I am confused how does objection mechanism work in this case? Its expected I raise and drop objection in both sequence?

uvm_config_db #(uvm_object_wrapper)::set(this,"envo.reset_agent_in.reset_seqr.reset_phase","default_sequence",reset_packet_sequence::get_type());
uvm_config_db #(uvm_object_wrapper)::set(this,"envo.transmit_agent_in.transmit_seqr.main_phase","default_sequence",transmit_packet_sequence::get_type());

In reply to aashishs2603:

You are raising the obejections before you start the first sequemce and you are dropping the objection after the last sequence has been completed in the test.
This just easy when using the run_phase. Working with the sub-phases makes it more complicated.
You should switch to the run_phase approach, starting the reset sequence first and continuing with the transmit sequence.
And please, do not use the default sequence approach. Startt the sequences manually.

In reply to chr_sue:

Just to confirm if I follow approach where I use start method to start sequence instead of config db 2nd method is recommended below?

phase.raise_objection(this);	
	reset_seq.start(envo.reset_agent_in.reset_seqr);
	phase.drop_objection(this);
        phase.raise_objection(this);	
	tx_seq.start(envo.tx_agent_in.tx_seqr);
	phase.drop_objection(this);
phase.raise_objection(this);
        reset_seq.start(envo.reset_agent_in.reset_seqr);
        tx_seq.start(envo.tx_agent_in.tx_seqr);
        phase.drop_objection(this);

In reply to aashishs2603:

Yes the 2nd method is recommended.

In reply to chr_sue:

Inside run_phase there are four different sub phases reset, config, main and shutdown. So do we need to bother about those phases when we call reset sequence in the middle of the test? I thought we need to jump back to the reset phase inside a run phase when we call reset seq. In general if we have got reset on the interface how should or what should be the best way to handle using these phases and which phases should be used.

Thank you,
Mega

In reply to megamind:

The rule is:
raise the objection befor the sequence activity starts and drop the objection when the activity has been completed.
I your case you are raing the objection in the rset_phase befor you are stating the reset sequence and youa re dropping the objection in the main_phase when the transmit sequence has been completed.

Thank you for the response.
I am asking about the scenario when transmit sequence is going on in the main_phase of run_phase and in between reset is observed by monitor, then should I go/jump back to the reset_phase? if yes then how? any example?

-Mega

In reply to megamind:

From your scenario I do not see you need reset_phase and main_phase.
You can run a reset_sequence and the transmit sequence. If you need a random reset you can do this using a randcase.
The recommendation is to avoid the sub-phases of the run_phase. You might end up in a critical situation.