Let me start by clarifying the question. I do not mean it in general (I am sure it is very useful in certain projects, above all in advanced microelectronics companies), but for simpler projects with less need for reusability and complex functionalities. And where engineers have a certain knowledge of UVM but not (at least no experience with) the register layer
Imagine:
1. you only use 1 interface to send write and read config to the chip
2. the protocol is defined and will not change substantially
3. you want to use the register model to make your UVM agents behave accordingly
4. you want to build a scoreboard to check what has been written matches what is read out
5. you would also like the scoreboard to access internal registers of the DUT (backdoor style) for an additional check
Can the 3.-5. points above not be achieved by UVM classes w/o the need of the register layer abstraction? My main doubts:
- I guess 3. could be achieved with the configuration database (as I understand also the reg layer does)
- and 5. may be (uglier) obtained with an interface (list of registers) or better through VPI.
For such a "simple" target, can anybody see a strong argument to add on top of the configuration agent a higher level of abstraction, which then needs in addition the adapter and predictor and a knowledge of the UVM register layer syntax, etc. (i.e. learning curve) ?
I would really appreciate suggestions and comments from people with more experience on the field.
Many thanks in advance.
