In reply to sarconi:
For such a “simple” target, can anybody see a strong argument to add on top of the configuration agent a higher level of abstraction, which then needs in addition the adapter and predictor and a knowledge of the UVM register layer syntax, etc. (i.e. learning curve) ?
I would really appreciate suggestions and comments from people with more experience on the field.
The key question is not a ‘simple project’. It is how many configuration registers do you have. If you have only 1 to 5 configuration registers it might be an overkill to use the RAL. In any other case it is very useful to deal with the RAL.
To ease the implementation you should use an UVM Framework Generator like the EasierUVM Code Generator from Doulos (see here https://www.doulos.com/knowhow/sysverilog/uvm/). It is free of charge.