In reply to rgarcia07:
There are some idiosyncrasies to using interface classes together with UVM. One of the most annoying I noticed is:
function do_stuff(some_interface_class arg);
// fails to compile, because 'print()' is defined in 'uvm_object' and 'arg' is of type
It's not possible to say that you have an object that both implements an interface (some_interface_class) and is a uvm_object.
Java has print() and clone() methods embedded in any_object, which every class implicitly extends, so an argument of type some_interface_class would also automatically get these methods. (Java terminology for the methods/classes in the sentence is toString(), clone() and Object, but I wanted to use something similar to the UVM names.)
C++ handles these common operations like printing and copying using operator overloading.
SystemVerilog provides neither of these two mechanisms. You end up having to declare all of your interfaces as printable, clonable, etc. which really defeats the point of using interface classes.