Simulation changing with respect to Sequence name

This is one of the test I am trying to run

class simpleme_test extends base test; 
//Registering test 
'uvm_component_utils(simpleme_test) 
function new(string name, uvm_component parent);
 super.new(name, parent); 
 endfunction : new

//Declare the sequence
 simple_sequence seq; 

//simpleme class methods 
extern virtual task main_phase(uvm_phase phase); 
endclass : simple_test

task simple_test mainphase(uvm_phase phase); 
seq = simpleme_sequence::type_id::create( "SEQ");
  phase. raise_objection(this); 
  'uvm_info(get_full_name(), $sformatf("Running SIMPLE TEST"), UVM_MEDIUM) 
  seq.start(m_env.m_agent.m_sequencer);
  phase.drop_objection(this);
endtask : main_phase

When I try to run this code, The simulation was hanging. But when I changed the sequence name from “SEQ” to “simple_sequence”, it’s working. With a different name it’s giving different simulation behaviour.
Can anyone point out the possible reasons?

In reply to bachan21:

I have corrected some Syntex error from your code and tried below code it’s working fine for me with “SEQ” or “simple_sequence”.
So, there is not issue of name “SEQ” or “simple_sequence”.
name is only just use to create object only.



// Code your testbench here
// or browse Examples

`include "uvm_macros.svh"
import uvm_pkg::*;

class simple_sequence extends uvm_sequence;
  `uvm_object_utils(simple_sequence)
  
  function new(string name="");
    super.new(name);
  endfunction : new
  
  virtual task body();
    $display("CHECK PASS");
  endtask : body
  
endclass : simple_sequence

class simple_test extends uvm_test; 
//Registering test 
  `uvm_component_utils(simple_test)
  
function new(string name, uvm_component parent);
 super.new(name, parent); 
 endfunction : new
 
//Declare the sequence
 simple_sequence seq; 
 
//simpleme class methods 
extern virtual task main_phase(uvm_phase phase); 
endclass : simple_test
 
task simple_test::main_phase(uvm_phase phase); 

//simpl_sequence
  seq = simple_sequence::type_id::create("simple_sequence");
  
// SEQ
//seq = simple_sequence::type_id::create( "SEQ");

  phase. raise_objection(this); 
  `uvm_info(get_full_name(), $sformatf("Running SIMPLE TEST"), UVM_MEDIUM) 
  seq.start(null);
  phase.drop_objection(this);
endtask : main_phase
  
module m;
  initial begin
    run_test("simple_test");
  end
endmodule : m


Thanks!

In reply to harsh pandya:

Hi Harsh,

The header file inclusion and import is done in my top file. I didn’t mention as it’s a normal process. Another fact is I can’t start my sequence on null. I have a specific sequencer to run this sequence.

I observe different results with respect to different sequence name. I am assuming it’s some uvm library error. I am trying to figure out that one.

-Shyam

In reply to bachan21:

If you look into my code carefully. I have not only added header files.
Below are compile issue in your code as well.

  1. macros can call via `not ’
  2. task declaration outside the class required classname::methodname which is missing.
    And “main_phase” will be like this (However you have write as mainphase)
  3. you have declare sequence handle seq from “simple_sequence” however while in at create you use “simpleme_sequence”.

And regarding sequencer, in my code I have not used sequencer so I pass as null.
If, you pass sequencer then it will not make any difference when you have sequencer.

And i grep in uvm base class, and I didn’t find anything with name “SEQ”.
So,I have doubt on that library is cause for your hang issue.

Will you please share your complete code over EDA if possible.
Then someone can might help you to figured out actual issue.

Thanks!