Simulation changing with respect to Sequence name

UVM
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2

In reply to bachan21:

I have corrected some Syntex error from your code and tried below code it’s working fine for me with “SEQ” or “simple_sequence”.
So, there is not issue of name “SEQ” or “simple_sequence”.
name is only just use to create object only.



// Code your testbench here
// or browse Examples

`include "uvm_macros.svh"
import uvm_pkg::*;

class simple_sequence extends uvm_sequence;
  `uvm_object_utils(simple_sequence)
  
  function new(string name="");
    super.new(name);
  endfunction : new
  
  virtual task body();
    $display("CHECK PASS");
  endtask : body
  
endclass : simple_sequence

class simple_test extends uvm_test; 
//Registering test 
  `uvm_component_utils(simple_test)
  
function new(string name, uvm_component parent);
 super.new(name, parent); 
 endfunction : new
 
//Declare the sequence
 simple_sequence seq; 
 
//simpleme class methods 
extern virtual task main_phase(uvm_phase phase); 
endclass : simple_test
 
task simple_test::main_phase(uvm_phase phase); 

//simpl_sequence
  seq = simple_sequence::type_id::create("simple_sequence");
  
// SEQ
//seq = simple_sequence::type_id::create( "SEQ");

  phase. raise_objection(this); 
  `uvm_info(get_full_name(), $sformatf("Running SIMPLE TEST"), UVM_MEDIUM) 
  seq.start(null);
  phase.drop_objection(this);
endtask : main_phase
  
module m;
  initial begin
    run_test("simple_test");
  end
endmodule : m

Thanks!