$sdf_annotate in a Testbench

UVM
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1

Hi everyone,

I saw some codes given below. They call $sdf_annotate(xxx.sdf, inst_name.DUV). I could not understand why. SDF is a file including timing informations and delay. Why would we need to call a sdf file for verification?

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In the initial stages of your design you will be performing “functional” simulations to ensure the logic in your circuit operates correctly. After your FPGA or ASIC tools generate a layout for your gate-level design, you may want to perform a final simulation with back-annotated timing information generated during the layout process to account for real world interconnect and gate delays. This “timing” simulation is often used as a final check to ensure that unexpected delays generated during the layout process don’t create timing violations in your design. The layout tools will create a Standard Delay File (SDF) that includes this timing information

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initial begin 

`ifdef TIMING_SIM

$sdf_annotate(a_project//design/netlist/xx_top.sdf", AL_0.DUV)

`endif

end
2

In reply to hcglu:

The Standard Delay Formant (SDF) is an IEEE standard (1497-2001) intended to be used with many HDL and other gate-level netlist languages. SDF is independent of source language, although almost all gate-level netlists today are in Verilog.

Having the SDF in a separate file also makes it easier for tools to read in a netlist then create a file with just the timing information and not have to output a redundant netlist.

3

In reply to dave_59:

Thank you Dave. Your answer is so informative but I could not understand that. I saw these code given above in a UVM based verification environment. What is the advantage of using these file in such a verification environment? Why did choose that?

Thanks,
Hakan