$sdf_annotate in a Testbench

In reply to hcglu:

The Standard Delay Formant (SDF) is an IEEE standard (1497-2001) intended to be used with many HDL and other gate-level netlist languages. SDF is independent of source language, although almost all gate-level netlists today are in Verilog.

Having the SDF in a separate file also makes it easier for tools to read in a netlist then create a file with just the timing information and not have to output a redundant netlist.