[RAL] Monitoring write and read transactions with a protocol that works in two cycles

UVM
,
1

Hi,

I have a protocol that writes in one cycle but takes two cycles to issue a read.
The code that notifies the transaction to the adapter is the following:


interface dbg_monitor_bfm
(
    input logic clk_i,

    input logic re_i,
    input logic we_i,
    input logic [DBG_ADDR_WIDTH-1:0] address_i,
    input logic [DBG_DATA_WIDTH-1:0] write_data_i,

    input logic [DBG_DATA_WIDTH-1:0] read_data_o
);


    dbg_monitor proxy;

    task run();
        dbg_seq_item item;
        dbg_seq_item cloned_item;
        bit was_a_read;
        was_a_read = 0;

        forever begin
            if (!was_a_read)
                @(posedge clk_i);
            else begin
                was_a_read = 0;
            end

            if (dbg_we_i) begin
                item = dbg_seq_item::type_id::create("item");
                item.we = we_i;
                item.re = 0;
                item.addr = address_i;
                item.data = write_data_i;

                proxy.notify_transaction(item);
            end
            else if (dbg_re_i) begin
                item = dbg_seq_item::type_id::create("item");
                was_a_read = 1;

                item.we = 0;
                item.re = re_i;
                item.addr = address_i;

                @(posedge clk_i);
                item.data = read_data_o;

                proxy.notify_transaction(item);
            end
        end

    endtask : run 

endinterface : dbg_monitor_bfm

This works in the sense that it is capable of notifying the transaction but then the uvm_reg_map finishes later and does not take the correct value (that’s what I could see with the debugger). I think the main problem is that I have to wait for a cycle to get the read value from the registers but I do not know how to do it just in one cycle. I tried to adapt this code to work on the negative edge of re_i and we_i; Transactions were notified correctly but then the uvm_reg_map would wait until the next notified transaction after a lot of cycles (whenever there is a re_i or we_i negative edge).

So, do you think is it possible to do it in one cycle? Is there something that I am missing?

Thanks!!
Marc

2

In reply to Marc43:

I solved this.

I had the wrong conception of how the value is read. In reality, it is from the driver’s sequence that uvm_reg_map gets the read value. You have to assign the readen value to the sequence data.

This also has some problems in my case but it is as easy as distinguishing between the read and write cases when driving. If it is a write, spend one cycle, if it is a read, spend two cycles and assign the readen value to the sequence.