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  • Passing TB/RTL parameters to sequences

Passing TB/RTL parameters to sequences

UVM 6946
DUT parameters 3 #ParameterizedClass 10
Suman Patra
Suman Patra
Full Access
2 posts
November 09, 2020 at 12:42 am

If the design has N ports and N can be changed as per the product requirement, then how do we get this port information N in the generic sequences that we code to validate such a design. The design uses parameters, which I have in the TB and interface also. In the sequences and other TB components, we need a lot of port-based variable declaration. How do we achieve this passing of a parameter? Or is there any other way to accomplish this?

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chr_sue
chr_sue
Full Access
3992 posts
November 09, 2020 at 8:39 am

In reply to Suman Patra:

If you have a SV design and a SV/UVM testbench it is just easy to solve this problem. You can these parameters to a SV package and import it in the design as well as the testbench. In the testbench you can pass the parameters to the config_db and retrieve them in any place you need them.
If you have mixed language situation, i.e. VHDL design and a SV/UVM environment it becomes complicated . Simulators might offer packages to be used in both language worlds.

Suman Patra
Suman Patra
Full Access
2 posts
November 12, 2020 at 8:33 pm

In reply to chr_sue:

I need these parameters to create class variables with array index of N(number of ports). So, the information has to be passed to the class using parameters. How do I use config_db to serve this purpose?

chr_sue
chr_sue
Full Access
3992 posts
November 14, 2020 at 9:39 am

In reply to Suman Patra:

You could store the parameters in a package and import the package in any place where you need these parameters. This would be the most simple solution.

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