In reply to Suman Patra:
If you have a SV design and a SV/UVM testbench it is just easy to solve this problem. You can these parameters to a SV package and import it in the design as well as the testbench. In the testbench you can pass the parameters to the config_db and retrieve them in any place you need them.
If you have mixed language situation, i.e. VHDL design and a SV/UVM environment it becomes complicated . Simulators might offer packages to be used in both language worlds.