Monitoring of RO Registers in UVM

UVM
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1

Hi,

I’m trying to monitor a Read only Register for some changes.But I’m not getting a proper solution as the value of the reg is defined by some other internal signals.

I tried the wait_for_change method with RAL, where we have to use the rtl path.But got some error:
“Remove hierarchical reference from the package.****”
I can remove this error.But is there any other alternative solution to monitor these type of status registers.

Thanks,
Aji

2

In reply to ajithomas003:

You cannnot use constructs like this in a package. But you can do this from outside, especially from the toplevel of your testbench.

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In reply to chr_sue:

In reply to ajithomas003:
You cannnot use constructs like this in a package. But you can do this from outside, especially from the toplevel of your testbench.

Thanks @chr_sue for the reply.I tried with that.

Is there any alternative way to monitor the STATUS registers,whose value is completely defined by some internal signals.I have one scenario,where I need to trigger some actions based on a status register which having RO policy.

How we can verify such registers through UVM

4

In reply to ajithomas003:

Finally you do not know when the register content changes. You could add a uvm_event to your SV interface. Then you can trigger your actions on this event.
For verification of RO registers you can you the backdoor access, because this is not restricted to the access policy. Best is to use peek and poke for reading and writing such registers.