In reply to chr_sue:
In reply to ajithomas003:
You cannnot use constructs like this in a package. But you can do this from outside, especially from the toplevel of your testbench.
Thanks @chr_sue for the reply.I tried with that.
Is there any alternative way to monitor the STATUS registers,whose value is completely defined by some internal signals.I have one scenario,where I need to trigger some actions based on a status register which having RO policy.
How we can verify such registers through UVM