I get:
Warning-[ISVSIVI] Illegal SystemVerilog construct …/…/tb/cg_axi_if_types.svh, 22 cg_axi_slave_if
Interfaces with parameterized interface ports may not be used as virtual interfaces.
The line 22 of cg_axi_if_types.svh that compiler is complaining about is:
typedef virtual interface cg_axi_slave_if #(.ADDR_WIDTH(ADDR_WIDTH),.DATA_WIDTH( MEM_DWIDTH),.ID_WIDTH(ID_WIDTH),.USER_WIDTH(USER_WIDTH)) cg_axi_slave_vif_t;
The definition of interface cg_axi_slave_if is:
interface cg_axi_slave_if #(ADDR_WIDTH=32, DATA_WIDTH=64, ID_WIDTH=6, USER_WIDTH=1)
(
input logic clk ,
input logic resetn,
cg_axi_if.target in_if
);
Sure enough, port cg_axi_if.target in_if is a parameterized interface.
The definition of cg_axi_if is:
interface cg_axi_if #(ADDR_WIDTH=32, DATA_WIDTH=64, ID_WIDTH=6, USER_WIDTH=1);
My designers created their interface cg_axi_if I discussed above.
They asked me to create a slave responder model they could attach to any of their cg_axi_if instances (for modelling).
I created the cg_axi_slave_if which takes their interface as a port and wiggles the pins responding to the AXI protocol as a slave responder.
Within cg_axi_slave_if, the memory is modeled as an associative array. I created backdoor array access methods to access from
my UVM testbench. I’m using the uvm_config_db to pass the cg_axi_slave_if handle as a virtual interface to by testbench.
Even though we get this warning, the testbench is working well.
I’d like to work around this warning.
In reply to cturner:
I believe your problem is in your SV interface. The syntax is as follows:
interface (<possible arguments, have to have the same data direction in all modules connected to>);
list of all signals belonging to that interface;
endinterface
If you are using parameters you have to specify the actual values.
In reply to chr_sue:
Thank you for your thoughts on that.
You have shown one syntax for an interface definition.
Another valid syntax is as below:
interface simple_bus #(AWIDTH = 8, DWIDTH = 8) (input logic clk);
list of signals
endinterface
I grabbed part of the above example from p730 of SV Standard doc.
In my situation, instead of input logic clock, I have an interface as a port.
The problem comes because the interface I have as a port is parameterized.
In reply to cturner:
The syntax you are showing has parameters. That is valid of course.
But an interface cannot have another interface as port. But you might instantiate another interface inside your interface construct. An interface argument needs always a data direction. The SV does not have one.
In reply to chr_sue:
In reply to cturner:
The syntax you are showing has parameters. That is valid of course.
But an interface cannot have another interface as port. But you might instantiate another interface inside your interface construct. An interface argument needs always a data direction. The SV does not have one.
This is incorrect. An interface port list declaration can have all the same constructs as a module port list declaration.
The problem comes from the fact that you cannot specify parameter overrides in an interface port—it absorbs whatever overrides that get connected to instance. Since parameters can effect the types of things you reference through a virtual interface, all parameters must match. There’s no way to guarantee the parameters match because you can have the same interface instantiated multiple times, with each interface instance connected to different interfaces.
In your case, as long as you only reference items through your virtual interface that are not effected by parameterization, you can ignore the warning.
In reply to dave_59:
Thanks Dave.
From my TB, I do access virtual interface members connected by the port which input parameterized interface. I also make assumptions that the parameterization is consistent.
I think I’m getting away with this because we have a common set of parameters used by both the design and the testbench teams.
However, I think I can check my assumption of consistent parameterization.
I added the following size consistency check:
interface cg_axi_slave_if #(ADDR_WIDTH=32, DATA_WIDTH=64, ID_WIDTH=6, USER_WIDTH=1)
(
input logic clk ,
input logic resetn,
cg_axi_if.target in_if
);
initial begin
if ($size(in_if.aw_addr) != ADDR_WIDTH) begin $error(“size(in_if.aw_addr):%0x doesn’t match ADDR_WIDTH:%0x”,$size(in_if.aw_addr),ADDR_WIDTH); end
if ($size(in_if.w_data ) != DATA_WIDTH) begin $error(“size( in_if.w_data):%0x doesn’t match DATA_WIDTH:%0x”,$size(in_if.w_data ),DATA_WIDTH); end
end