In reply to chr_sue:
Thank you for your thoughts on that.
You have shown one syntax for an interface definition.
Another valid syntax is as below:
interface simple_bus #(AWIDTH = 8, DWIDTH = 8) (input logic clk);
list of signals
endinterface
I grabbed part of the above example from p730 of SV Standard doc.
In my situation, instead of input logic clock, I have an interface as a port.
The problem comes because the interface I have as a port is parameterized.