Hi chr_sue,
As per your suggestion we have done but still we are getting errors, for other files there are same errors but for the interface and package the error is different. Here we have attached agent, package and interface code along with the Errors.
Let us know what we are doing is right or wrong and this should be done in questasim if anyone has done any UVM example using questasim kindly share the example and procedure to do it in the questasim.
Agent Code:
package apb_pkg;
import uvm_pkg::*; //import umv_pkg::*;
`include "uvm_macros.svh"
typedef class agent;
typedef class sequencer;
typedef class driver;
typedef class monitor;
class agent extends uvm_agent;
`uvm_component_utils(agent)
sequencer system_sqncr;
driver system_driv;
monitor system_mon;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction: new
////////////// BUILD PHASE //////////////////////////////
function void build_phase(uvm_phase phase);
super.build_phase(phase);
//ACTIVE
system_sqncr=sequencer::type_id::create("system_sqncr",this);
system_driv=driver::type_id::create("system_driv",this);
system_mon=monitor::type_id::create("system_mon",this);
endfunction: build_phase
////////////// CONNECT PHASE //////////////////////////////
function void connect_phase(uvm_phase phase);
system_driv.seq_item_port.connect(system_sqncr.seq_item_export);
endfunction: connect_phase
endclass: agentPackage File:
package apb_pkg;
// Imports
import uvm_pkg::*;
`include "uvm_macros.svh"
// UVC includes
`include "apb_seq_item.sv"
`include "apb_sequence.sv"
`include "apb_sequencer.sv"
`include "apb_driver.sv"
`include "apb_monitor.sv"
`include "apb_agent.sv"
`include "apb_scoreboard.sv"
`include "apb_environment.sv"
`include "apb_test.sv"
`include "apb_Testbench_Top.sv"
`include "apb_interface.sv"
endpackage
Interface File:
package apb_pkg;
import uvm_pkg::*; //import umv_pkg::*;
`include "uvm_macros.svh"
typedef class interface;
interface system_inf( input logic clk, resetn);
//logic clk;
//logic resetn;
logic pcpi_valid;
logic [31:0]pcpi_insn;
logic [31:0]pcpi_rs1;
logic [31:0]pcpi_rs2;
logic pcpi_wr;
logic [31:0]pcpi_rd;
logic pcpi_wait;
logic pcpi_ready;
logic trap;
clocking driver_cb @(posedge clk);
default input #1 output #1;
//output clk;
//output resetn;
output pcpi_valid;
output pcpi_insn;
output pcpi_rs1;
output pcpi_rs2;
output pcpi_wr;
output pcpi_rd;
output pcpi_wait;
output pcpi_ready;
input trap;
endclocking
clocking monitor_cb @(posedge clk);
default input #1 output #1;
input clk;
input resetn;
input pcpi_valid;
input pcpi_insn;
input pcpi_rs1;
input pcpi_rs2;
input pcpi_wr;
input pcpi_rd;
input pcpi_wait;
input pcpi_ready;
input trap;
endclocking
modport DRIVER (clocking driver_cb, input clk,resetn);
modport MONITOR (clocking monitor_cb, input clk,resetn);
endinterface
Error for Agent file:
vlog -work work -vopt -sv -stats=none {D:\UVM_Package\apb_agent.sv}
QuestaSim-64 vlog 2021.4 Compiler 2021.10 Oct 13 2021
-- Compiling package apb_pkg
-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in)
** Note: (vlog-2286) D:\UVM_Package\apb_agent.sv(3): Using implicit +incdir+C:/Program Files (x86)/questa_sim-win64-2021.4/uvm-1.1d/../verilog_src/uvm-1.1d/src from import uvm_pkg
** Error: (vlog-13069) D:\UVM_Package\apb_agent.sv(36): near "EOF": syntax error, unexpected end of source code, expecting class.
Error for Package file:
vlog -work work -vopt -sv -stats=none D:/UVM_Package/apb_pkg.sv
QuestaSim-64 vlog 2021.4 Compiler 2021.10 Oct 13 2021
-- Compiling package apb_pkg
-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in)
** Note: (vlog-2286) D:/UVM_Package/apb_pkg.sv(7): Using implicit +incdir+C:/Program Files (x86)/questa_sim-win64-2021.4/uvm-1.1d/../verilog_src/uvm-1.1d/src from import uvm_pkg
** Error: (vlog-13069) ** while parsing file included at D:/UVM_Package/apb_pkg.sv(11)
** at apb_seq_item.sv(1): near "package": syntax error, unexpected "SystemVerilog keyword 'package'", expecting class.
Error for Interface file:
vlog -work work -vopt -sv -stats=none {D:\UVM_Package\apb_interface.sv}
QuestaSim-64 vlog 2021.4 Compiler 2021.10 Oct 13 2021
-- Compiling package apb_pkg
-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in)
** Note: (vlog-2286) D:\UVM_Package\apb_interface.sv(4): Using implicit +incdir+C:/Program Files (x86)/questa_sim-win64-2021.4/uvm-1.1d/../verilog_src/uvm-1.1d/src from import uvm_pkg
** Error: (vlog-13069) D:\UVM_Package\apb_interface.sv(6): near "interface": syntax error, unexpected "SystemVerilog keyword 'interface'", expecting IDENTIFIER or TYPE_IDENTIFIER or NETTYPE_IDENTIFIER.
