Error: Class data is not allowed in non-procedural context

UVM
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1

I know in UVM I should use interface to pass values to dut but I am doing very small test and I need to directly drive signals of DUT. I see effect of first two force statements but in the third force statement which is inside loop it gives this error. How can I solve this kind of error?

class test_1 extends base_test;
`uvm_component_utils(test_1)

int i;
.......
.......

 task run_phase(uvm_phase phase);
     super.run_phase(phase); 
     phase.raise_objection(this);
  begin
    #10;
    force `Path_to_Block.dut_signal_mode_1 = 1'b1;
    #10
    force `Path_to_Block.dut_signal_mode_1 = 1'b0;

    for(i = 0; i < 36; i=i+1) begin
      #2
      force `Path_to_Block.packet_data_in = (1'b1 << i);
    end
  end
     phase.drop_objection(this);
 endtask : run_phase
endclass : test_1
2

In reply to vickydhudashia92:
The signals involved in a force statement must be wires or static variables. Change to

static int i;

and I would change i to something more unique so it is only used for that purpose, like shift_left.

3

In reply to dave_59:

Thank you dave. That worked.

4

In reply to dave_59:

Hi Dave,

I got a similar problems with force statement.
I have an array in the DUT which is declared as follow


module mem_model;
reg [255:0] mem [0:2047];
...
endmodule

And in a certain test sequence, I need to force that mem[2048] array one at a time, so I did the following in my test


class my_uvm_sequence extends my_uvm_sequence_base;
...
  static int mem_index=0;
...
  task body();
    ...
    for(mem_index=0;mem_index<2048;mem_index++)begin
      force `MY_DUT_PATH.mem_model.mem[mem_index][1:0]=2'b00;
      ...
    end
  endtask
endclass

However I got the following compilation error from my simulator (VCS 2017)

Error-[SV-FNYI] Feature not yet implemented
SystemVerilog feature not yet implemented. Assign/deassign/force/release on
a static class member. Expression: this.mem_index

I wonder I got this error is simply because my vendor is out-of-date or the way I am forcing is incorrect by itself?

If my force statement is incorrect, I wonder is there a neat way to force an array element one at time instead of unrolling the loop and write the force statement manully for 2k times?

Thanks in advance for your help!

5

In reply to peterjin:
Cannot help you with an unsupported error, but your code would not work they way you want to anyways. A force sets up a continuous assignment from RHS to LHS, and the LHS cannot contain non-constant part selects. The LRM does not allow part selects to variables, But most tools allow it. Also, if you put this class in a package, you are not allowed to have hierarchical references to your DUT.

What I suggest you do is put the force into an interface that you bind inside your module mem_model. Then you can use a generate-for loop to create individual force statements.

interface insert_force;
  bit enable;

  for (genvar index=0;index<2048;index++)
    always @(enable)
      if (enable)
        force mem[index][1:0] = 0;
      else 
        release mem[index][1:0];
endinterface
6

In reply to dave_59:

Thanks for your help!

Peter