Error: Class data is not allowed in non-procedural context

UVM
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4

In reply to dave_59:

Hi Dave,

I got a similar problems with force statement.
I have an array in the DUT which is declared as follow


module mem_model;
reg [255:0] mem [0:2047];
...
endmodule

And in a certain test sequence, I need to force that mem[2048] array one at a time, so I did the following in my test


class my_uvm_sequence extends my_uvm_sequence_base;
...
  static int mem_index=0;
...
  task body();
    ...
    for(mem_index=0;mem_index<2048;mem_index++)begin
      force `MY_DUT_PATH.mem_model.mem[mem_index][1:0]=2'b00;
      ...
    end
  endtask
endclass

However I got the following compilation error from my simulator (VCS 2017)

Error-[SV-FNYI] Feature not yet implemented
SystemVerilog feature not yet implemented. Assign/deassign/force/release on
a static class member. Expression: this.mem_index

I wonder I got this error is simply because my vendor is out-of-date or the way I am forcing is incorrect by itself?

If my force statement is incorrect, I wonder is there a neat way to force an array element one at time instead of unrolling the loop and write the force statement manully for 2k times?

Thanks in advance for your help!