Hello,
I have the following scenario: I have a testbench which instantiates a DUT and two UVM tests (classes). The DUT has two interfaces:
- Interface_1 is connected to the UVM tests via a virtual interface. The sequences will drive signals on this interface.
- Interface_2 should connect the DUT to one of two verilog modules, depending on which UVM test is selected. So for UVM-test-A the Interface_2 should be connected to Verilog-module-A and for UVM-test-B the Interface_2 should be connected to Verilog-module-B.
First I thought I could do that by instantiating the specific Verilog module in each test class. But that didn´t work and after some search I found that it´s not possible to instantiate modules in classes.
Are there other possibilities to do this?
I found a thread where somebody mentioned using a multiplexer that connected the DUT to both Verilog modules and that was controlled by the UVM-tests. I assume this chould work, but maybe there is a better solution?
Thank you for your help.
Antonio
