Connecting a DUT to different Verilog modules from within UVM

UVM
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1

Hello,

I have the following scenario: I have a testbench which instantiates a DUT and two UVM tests (classes). The DUT has two interfaces:

  • Interface_1 is connected to the UVM tests via a virtual interface. The sequences will drive signals on this interface.
  • Interface_2 should connect the DUT to one of two verilog modules, depending on which UVM test is selected. So for UVM-test-A the Interface_2 should be connected to Verilog-module-A and for UVM-test-B the Interface_2 should be connected to Verilog-module-B.

First I thought I could do that by instantiating the specific Verilog module in each test class. But that didn´t work and after some search I found that it´s not possible to instantiate modules in classes.
Are there other possibilities to do this?

I found a thread where somebody mentioned using a multiplexer that connected the DUT to both Verilog modules and that was controlled by the UVM-tests. I assume this chould work, but maybe there is a better solution?

Thank you for your help.
Antonio

2

In reply to Antonio:

I believe you understanding of the UVM architecture is wrong. You will never connect a test to your DUT. A test is configuring your UVM testbench and starting the processing of sequences generating sequence items and analysing simulation data with respect to functional coverage, assertion and correctness of the simulation data.
Your inreface connects the DUT with your UVM testbench. Depending on the nummber of functional interfaces you have a certain number of agents in the UVM environment. These agents are also connected to your interface.

3

In reply to chr_sue:

Ah ok, sorry, maybe I didn´t describe the situation correctly. In my testbench, I instantiated a DUT, a virtual interface and use run_test() to run the UVM test. The UVM test contains a UVM environment which contains a UVM agent which contains a UVM driver. The driver is connected to the virtual interface, which is connected to the DUT. When drawing that onto a paper, it looks like the connection between driver and DUT is going through the boundaries of the other classes (like “test”).
But you are right indeed, it´s just connecting the driver and the DUT.

4

In reply to Antonio:

To correct your wording.
(1) The toplevel module contains on or more SystemVerilog interfaces.
(2) A driver has a virtual interface which is of the type of one of your SystemVerilog interfaces.

You can pass the SystemVerilog interface to the configuration db using uvm_congig_db set.
From any other place in your UVM environment you can retrieve the SV interfaces passed to the configuration db by performing a uvm_config_db get command.