In reply to Antonio:
I believe you understanding of the UVM architecture is wrong. You will never connect a test to your DUT. A test is configuring your UVM testbench and starting the processing of sequences generating sequence items and analysing simulation data with respect to functional coverage, assertion and correctness of the simulation data.
Your inreface connects the DUT with your UVM testbench. Depending on the nummber of functional interfaces you have a certain number of agents in the UVM environment. These agents are also connected to your interface.