Add extra information to uvm_reg_bus_op

UVM
,
1

While I am doing RAL for my project, I come across an issue. The issue is, inorder to write into the register, I need to use few more signals other than data_in, addr, kind, byte_enable. How should I add those signals?

2

In reply to kireeti1192:

You could implement this in your adapter, it will use uvm_reg_item and this contains the extension which can be used to pass extra information that is specific to your implementation

Something like this

virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
  apb_info_h apb_info;
  uvm_reg_item item = get_item();
...
  bus_trans.addr = rw.addr;
  bus_trans.data = rw.data;
  if (item.extension != null) begin
    $cast(apb_info, item.extension);
    bus_trans.apb_info = apb_info;
  end
return bus_trans;
endfunction: reg2bus

There are several examples available on-line that may be able to give you an idea

HTH,

3

In reply to rgarcia07:

Thank you for the information. Can you provide an example for bus2reg method when few more signals other than data_in, kind, byte_enable and addr are used.

In my project, I have selection signal which is a randomized signal driven from the sequence. I want to add this signal to the write method parameters in ral_sequence.

Eg::
class transaction;
rand int addr;
rand int data;
rand bit we;
rand bit[3:0] sel;
endclass

class adapter extends uvm_reg_adapter;

virtual function void bus2reg(uvm_sequencer_item bus_item,
uvm_reg_bus_op rw);
seq_item item;
if (!$cast(item,bus_item)) begin
`uvm_fatal(“CONVERT_SEQITEM2REG”,“Bus item is not of type seq_item”)
end
rw.kind = item.op==item::READ ? UVM_READ : UVM_WRITE;
rw.addr = item.addr;
rw.data = item.data;
rw.status = UVM_IS_OK;
//???//
//For selection signal to be transmitted, what should be written here?//

endfunction

endclass

4

In reply to kireeti1192:

In reply to rgarcia07:
Thank you for the information. Can you provide an example for bus2reg method when few more signals other than data_in, kind, byte_enable and addr are used.
In my project, I have selection signal which is a randomized signal driven from the sequence. I want to add this signal to the write method parameters in ral_sequence.
Eg::
class transaction;
rand int addr;
rand int data;
rand bit we;
rand bit[3:0] sel;
endclass
class adapter extends uvm_reg_adapter;
virtual function void bus2reg(uvm_sequencer_item bus_item,
uvm_reg_bus_op rw);
seq_item item;
if (!$cast(item,bus_item)) begin
`uvm_fatal(“CONVERT_SEQITEM2REG”,“Bus item is not of type seq_item”)
end
rw.kind = item.op==item::READ ? UVM_READ : UVM_WRITE;
rw.addr = item.addr;
rw.data = item.data;
rw.status = UVM_IS_OK;
//???//
//For selection signal to be transmitted, what should be written here?//
endfunction
endclass

There are several questions I have regarding to your needs, normally what I’ve seen is that you don’t need to put extra info in the bus2reg method, since the idea is just to convert the specific transaction into a generic uvm_reg_bus_op.:
1- Why do you need to add it to the bus2reg?
2- Are you using explicit prediction? If yes you could use write method of the predictor along with register field callbacks to attach the info into the extension argument and in the register field callbacks (i.e: post_predict) you could finally decide if the value is to be written to the reg field(s), keep in mind that the predictor seats and observes the bus activity to decide what should happen (calling predict method in the end I believe)
2a- If you don’t know what explicit prediction is you can look a this

https://www.doulos.com/knowhow/sysverilog/uvm/aliased_registers/

The simplest thing I can think of is:

class m_predictor extends uvm_reg_predictor #(apb_item);

  virtual function void write(apb_item tr);
    if (apb_item.addr inside {[valid_range]})
     write(tr);//transaction is accepted
  endfunction
endclass