The uvm_reg_predictor class defines a predictor component, which is used to update the register model’s mirror values based on transactions explicitly observed on a physical bus.
| Explicit Register Predictor | |
| The uvm_reg_predictor class defines a predictor component, which is used to update the register model’s mirror values based on transactions explicitly observed on a physical bus. |
Updates the register model mirror based on observed bus transactions
This class converts observed bus transactions of type BUSTYPE to generic registers transactions, determines the register being accessed based on the bus address, then updates the register’s mirror value with the observed bus data, subject to the register’s access mode. See uvm_reg::predict for details.
Memories can be large, so their accesses are not predicted.
| uvm_reg_predictor | |||||||||||||||||
| Updates the register model mirror based on observed bus transactions | |||||||||||||||||
| Class Hierarchy | |||||||||||||||||
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| Class Declaration | |||||||||||||||||
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| Variables | |||||||||||||||||
| bus_in | Observed bus transactions of type BUSTYPE are received from this port and processed. | ||||||||||||||||
| reg_ap | Analysis output port that publishes uvm_reg_item transactions converted from bus transactions received on bus_in. | ||||||||||||||||
| map | The map used to convert a bus address to the corresponding register or memory handle. | ||||||||||||||||
| adapter | The adapter used to convey the parameters of a bus operation in terms of a canonical uvm_reg_bus_op datum. | ||||||||||||||||
| Methods | |||||||||||||||||
| new | Create a new instance of this type, giving it the optional name and parent. | ||||||||||||||||
| pre_predict | Override this method to change the value or re-direct the target register | ||||||||||||||||
| check_phase | Checks that no pending register transactions are still queued. | ||||||||||||||||
uvm_analysis_imp #( BUSTYPE, uvm_reg_predictor #(BUSTYPE) ) bus_in
Observed bus transactions of type BUSTYPE are received from this port and processed.
For each incoming transaction, the predictor will attempt to get the register or memory handle corresponding to the observed bus address.
If there is a match, the predictor calls the register or memory’s predict method, passing in the observed bus data. The register or memory mirror will be updated with this data, subject to its configured access behavior--RW, RO, WO, etc. The predictor will also convert the bus transaction to a generic uvm_reg_item and send it out the reg_ap analysis port.
If the register is wider than the bus, the predictor will collect the multiple bus transactions needed to determine the value being read or written.
uvm_analysis_port #( uvm_reg_item ) reg_ap
Analysis output port that publishes uvm_reg_item transactions converted from bus transactions received on bus_in.
uvm_reg_map map
The map used to convert a bus address to the corresponding register or memory handle. Must be configured before the run phase.
uvm_reg_adapter adapter
The adapter used to convey the parameters of a bus operation in terms of a canonical uvm_reg_bus_op datum. The uvm_reg_adapter must be configured before the run phase.
function new ( string name, uvm_component parent )
Create a new instance of this type, giving it the optional name and parent.
virtual function void pre_predict( uvm_reg_item rw )
Override this method to change the value or re-direct the target register
virtual function void check_phase( uvm_phase phase )
Checks that no pending register transactions are still queued.
Updates the register model mirror based on observed bus transactions
class uvm_reg_predictor #( type BUSTYPE = int ) extends uvm_component
The uvm_void class is the base class for all UVM classes.
virtual class uvm_void
The uvm_object class is the base class for all UVM data and hierarchical classes.
virtual class uvm_object extends uvm_void
The uvm_report_object provides an interface to the UVM reporting facility.
class uvm_report_object extends uvm_object
The uvm_component class is the root base class for UVM components.
virtual class uvm_component extends uvm_report_object
Observed bus transactions of type BUSTYPE are received from this port and processed.
uvm_analysis_imp #( BUSTYPE, uvm_reg_predictor #(BUSTYPE) ) bus_in
Analysis output port that publishes uvm_reg_item transactions converted from bus transactions received on bus_in.
uvm_analysis_port #( uvm_reg_item ) reg_ap
Defines an abstract register transaction item.
class uvm_reg_item extends uvm_sequence_item
The map used to convert a bus address to the corresponding register or memory handle.
uvm_reg_map map
The adapter used to convey the parameters of a bus operation in terms of a canonical uvm_reg_bus_op datum.
uvm_reg_adapter adapter
Create a new instance of this type, giving it the optional name and parent.
function new ( string name, uvm_component parent )
Override this method to change the value or re-direct the target register
virtual function void pre_predict( uvm_reg_item rw )
Checks that no pending register transactions are still queued.
virtual function void check_phase( uvm_phase phase )
Update the mirrored and desired value for this register.
virtual function bit predict ( uvm_reg_data_t value, uvm_reg_byte_en_t be = -1, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_path_e path = UVM_FRONTDOOR, uvm_reg_map map = null, string fname = "", int lineno = 0 )
This class defines an interface for converting between uvm_reg_bus_op and a specific bus transaction.
virtual class uvm_reg_adapter extends uvm_object