Hi How can I do xor in assertion property? like- property checker(clk,enable,a,b,idx); @(posedge clk) (enable) |-> a[idx^b] === b; endproperty:checker it’s seem it do idx power b … Thanks

In reply to Junior : working as expected for me [image] EDA Playground Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser. module test(); bit clk; bit en; bit [3:0] a[8]; bit [3:0] b, exp_b[8]; bit [2:0] i…

In reply to Alokpati : Thanks guys for your help, seem that the issue was different. another query, I have 1 property, that I assert to it multiply times, and for some this working - (A) |-> ## [0:3] ($past(sig_1) === sig_2); and some didn’t have delay and this works fine - (A) |-> ## [0:3] s…

In reply to Junior : can you elaborate what is the exact scenario for which you want to write assertion?

In reply to Alokpati : I have a situation that between sig 1 & sig 2 there is a delay of 1 cycle. and for itm this assertion is working well: (A) |-> ## [0:3] ($past(sig_1) === sig_2); another scenario, is that the sig2 happened in the same cycle as sig 1 (A) |-> ## [0:3] sig_1 === sig_2; now w…

In reply to Junior : (A) |-> ## [0:3] $past(sig_1) === sig_2 || sig_1 === sig_2; Please start a new question with a new topic.

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XOR in assertion property

SystemVerilog

dave_59 June 12, 2022, 3:47pm 2

In reply to Junior:

You are using the correct operator (^) for XOR. The power operator is (******)