Wrong rounding the result of division

SystemVerilog
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1

I have the following asssignment :

predicted.y = ($signed(in_trx.xi) * $signed(in_trx.cos) - $signed(in_trx.xq) * $signed(in_trx.sin))/ (131072);
Where the type are:

   bit [15:0]  xi;
   bit [15:0]  xq;
   bit [15:0]  sin;
   bit [15:0]  cos; 
   bit signed [15:0]  y;

For the following input:

xi = -4, cos = 32766 xq = -4 sin = 0

I expected to get -1 (the result is -0.99993896484375), but for some reason I get 0.

Why?

2

In reply to saritr:

Two issues:

  1. You are attempting to do arithmetic with 16 bit vectors where the intermediate results exceed 16 bits. This will result in overflow conditions affecting your results.

  2. You are attempting to conduct floating point arithmetic with integers.

3

In reply to cgales:

So how can I do it?

4

In reply to saritr:

You need to read section 11.3 of the SystemVerilog LRM. It discusses arithmetic operations and will answer your questions.