Writing randomized data in a uvm_reg test

UVM
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6

In reply to chr_sue:

Iam following the same way,as yours.

uvm_status_e status;
uvm_reg registers[$];
reg_model = ral_sys_TOP::type_id::create("reg_model");

`uvm_info("body_ral_seq","Entered to body of wie_ral_basic_access_sequence", UVM_LOW);
reg_model.get_registers(registers, UVM_HIER);
$display("\n regmodel size : %0d",registers.size());
`uvm_info("get_full_name()",$psprintf("RAL registers = %p", registers), UVM_LOW);
foreach(registers[i]) begin
    if ((uvm_resource_db#(bit)::get_by_name({"REG::",registers[i].get_full_name()},"NO_REG_TESTS", 0) != null) || (uvm_resource_db#(bit)::get_by_name({"REG::",registers[i].get_full_name()},"NO_REG_ACCESS_TEST", 0) != null )) begin
             `uvm_info(get_type_name(), $psprintf("NO_REG_TESTS is defined for this register=%0h so ignore R/WR",registers[i]), UVM_LOW);
          end
    else begin
      $display("Inside Wie_ral_basic_access_sequence RAL write function");
      `uvm_info("Write function","Inside Wie_ral_basic_access_sequence RAL write function", UVM_LOW);
      wr_data=$random;
      registers[i].write(status, wr_data, .parent(this));
    end
end