Writing coverpoints using with clause

SystemVerilog
,
1

Hello ,
Iam getting this warning while creating the coverpoints for a signal using with clause.Iam also attaching the covergroup snippet for better understanding

Warning: (vsim-8858) After processing coverbin with/set expression, the values list associated with array bin ‘rs1_addr_bin’ in Coverpoint ‘rs1addr’ of Covergroup instance '/main/top/cg ’ has converged to empty list. The bin will be taken out of coverage calculation.

  covergroup decoder_cg @(posedge CLK);
option.per_instance=1;
   rs1addr: coverpoint intf.decoder_func_32[65:61] {
                   bins rs1_addr_bin[32] = { [0:31] } with (intf.decoder_func_32[50] == 1'b0);
   } 
    
rs2addr: coverpoint intf.decoder_func_32[60:56] {
                   bins rs2_addr_bin[32] = { [0:31] } with (intf.decoder_func_32[49:48] == 2'b0);
   } 
rdaddr:  coverpoint intf.decoder_func_32[55:51] {
			bins raddr_bin[32] ={[0:31]};
}
endgroup

where intf is the interface handle.

2

In reply to vinayks:

You need to show the declarations of all variables involved. Also realize that bin construction happens with covergroup construction. So we need to know the values at that time.

3

In reply to dave_59:

Thanks for the reply dave

module tb_top(CLK,RST_N) ;
interface my_intf intf(CLK,RST_N);
always @(posedge CLK)
intf.decoder_func_32= mktbsoc.soc.ccore.riscv.stage2.instance_decoder_func_32_2.decoder_func_32;

covergroup decoder_cg @(posedge CLK);
option.per_instance=1;
   rs1addr: coverpoint intf.decoder_func_32[65:61] {
                   bins rs1_addr_bin[32] = { [0:31] }with (intf.decoder_func_32[50] == 1'b0);
   } 
    
rs2addr: coverpoint intf.decoder_func_32[60:56] {
                   bins rs2_addr_bin[32] = { [0:31] } with (intf.decoder_func_32[49:48] == 2'b0);
   } 
rdaddr:  coverpoint intf.decoder_func_32[55:51] {
			bins raddr_bin[32] ={[0:31]};
}
endgroup
decoder_cg  cg=new();
initial
 begin
cg.sample();
end
endmodule

where decoder_func_32 is 66 bit wide.and iam capturing the values at every posedge and also sampling the coverage in the initial block written in the interface

interface my_intf(input bit CLK,RST_N);
logic [65:0]decoder_func_32;
endinterface
4

In reply to vinayks:

decoder_func_32 is 'x when constructing the covergroup. Did you mean to use iff instead of with?

5

In reply to dave_59:

okay dave during reset I will make that signal zero.
and is it allowed to use iff keyword instead of with clause ? if the iff condition turns out to be false ,then bins will be created? are they taken into consideration for coverage report?

6

In reply to vinayks:

If you make the signal 0, then the with expression is alway true and behaves the same as if it was not there. You cannot dynamically change the existance of a bin once the covergroup has been constructed. The iff expression dynamically enables sampling of the bin; it is always considered for coverage.

If you could explain what coverage you are trying to model, it would make it possible to suggest the best way to code it.

7

In reply to dave_59:

I would like to check the functionality or the values of that signal(and increment the bin counts) ,when 50th bit of that signal is zero

8

In reply to vinayks:

That is still not very clear, but it sounds like iff is what you want to use.

9

In reply to dave_59:

Thank you Dave,the problem is solved after replacing with by iff.
But still iam not clear when to use with clause.

10

In reply to vinayks:

See Get Ready for SystemVerilog 2012 - Verification Horizons

11

In reply to dave_59:

Okay I’ll go through this link, thanks once again Dave