Writing coverpoints using with clause

SystemVerilog
,
3

In reply to dave_59:

Thanks for the reply dave

module tb_top(CLK,RST_N) ;
interface my_intf intf(CLK,RST_N);
always @(posedge CLK)
intf.decoder_func_32= mktbsoc.soc.ccore.riscv.stage2.instance_decoder_func_32_2.decoder_func_32;

covergroup decoder_cg @(posedge CLK);
option.per_instance=1;
   rs1addr: coverpoint intf.decoder_func_32[65:61] {
                   bins rs1_addr_bin[32] = { [0:31] }with (intf.decoder_func_32[50] == 1'b0);
   } 
    
rs2addr: coverpoint intf.decoder_func_32[60:56] {
                   bins rs2_addr_bin[32] = { [0:31] } with (intf.decoder_func_32[49:48] == 2'b0);
   } 
rdaddr:  coverpoint intf.decoder_func_32[55:51] {
			bins raddr_bin[32] ={[0:31]};
}
endgroup
decoder_cg  cg=new();
initial
 begin
cg.sample();
end
endmodule

where decoder_func_32 is 66 bit wide.and iam capturing the values at every posedge and also sampling the coverage in the initial block written in the interface

interface my_intf(input bit CLK,RST_N);
logic [65:0]decoder_func_32;
endinterface