Writing a concise constraint for setting variable number of LSB's depending on another random variable

SystemVerilog
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1

As the statement says it all, I am looking for a concise way to write a constraint for setting variable number of LSB’s of a particular number (let’s say var) depending on another random variable(let’s say set_bits).
I thought to write as shown below, however, it says “Range width must be constant expression”
$countones(var[0 +: set_bits]) != 0;

2

In reply to rahulkumarbudhwani:

myVar < (1<<set_bits)
3

In reply to rahulkumarbudhwani:

class Packet#(int size=5);
  
  rand bit[size-1:0] number;
  rand int unsigned setBits;
  
  constraint SIZE{ setBits < size;}
  
  constraint NUMBER{number == (1<<setBits);}
  
  function void post_randomize();
    number=number-1;
  endfunction
  
  function void display();
    $display("LSB SetBits is %b",number);
  endfunction
  
  
endclass

module tb;
  
  Packet#(10) pkt;
  
  initial
    begin
      pkt=new();
      void'(pkt.randomize());
      pkt.display();
    end
  
endmodule