Write an assertion for checking whether global clock is working properly with out taking a relative clock

SystemVerilog
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2

In reply to bachan21:
Not clear as to what you mean by checking whether global clock is working properly.
If you mean that checking that it is toggling per required frequency, you can do something like the following:

 
module top; 
    timeunit 1ns/10ps;
     bit g_clk, clk, a, b;  
     global clocking clk_global @(posedge g_clk); endclocking
     default clocking cb_clk @ (posedge clk);  endclocking 
     let half_period=5ns; 
     initial forever #half_period g_clk=!g_clk;  
      
     always  @(posedge g_clk)  begin 
        clk <= ! clk; // derived clk 
     end 
     
    initial begin : b0
      bit got_gclk, done; 
       begin  : f_ever
        fork
          begin : one 
            @(g_clk); 
            got_gclk=1'b1; 
            done=1'b1; 
          end  : one 

          begin : two 
            #(half_period+1); 
            done=1'b1; 
          end : two
        join_none
        wait(done);
        a_gclk: assert(got_gclk); // g_clk is active
        got_gclk=1'b0; 
        done=1'b0; 
      end : f_ever        
    end  : b0

    initial begin 
       #100; 
       $finish;
    end 
 endmodule

Note: assertion: A statement that a given property is required to hold. An assertion is a “statement about a design’s intended behavior” (From Assertion-Based Design, Foster).
It can be written in many forms, SVA is one of them, but there are other approaches.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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