Write a monitor code for 5 stage pipeline in which if in 1st clk valid signal is high then in 2nd cycle signal1 goes high and in 3rd cycle signal 2 goes high and so on signal 3 and signal 4

UVM
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In reply to dave_59:

Hi Dave,

This is not an assignment but an interview question and I don’t need the exact monitor code but just the approach for the run phase task for monitor. I had come up with a solution that would look similar to a driver, because as per my understanding, in monitor, we just monitor the transactions, like whatever is coming from the interface, we store it in a new transaction variable and then call the write(txn) api.
but in this question, I was asked to change the signals in monitor. So, this is where i got confused.
Any insights on this?