In reply to ben@SystemVerilog.us:
Ben is there a way to check the aysnchronous part via reports ( $display() ) .
For example ::
// Within procedural blocks
always @( negedge rst_n , posedge clk )
begin
if ( ! rst_n ) begin
$display($time,,,"...") ; // Can report N check that reset was asynchronous
// Drive initial values to signals
end
else
begin
// Non - Reset Logic here
.............................
end
end
Similarly can we have a report specifically when the reset is asserted in the concurrent assertion ?