In reply to MayurKubavat:
In reply to ben@SystemVerilog.us:
@ben, your solution in given link looks good. But there also, declaring clocking variable as inout might be unnecessary.
Just replacing “logic” with “wire” in above code seem to have done the job!
interface intf(bit clock);
wire a; //logic a;
clocking drvCb @(posedge clock);
output a; //Can be driven through procedural block
endclocking
...
I disagree that “declaring clocking variable as inout might be unnecessary”
Decalaring it as inout maintains the integrety/signifance/role of that variable in its context.
Declaring it as output has the implication that the variable is constantly driven to a hard value (i.e., not tri-stated); it now called “fake news” :).
Quote:
1800-2012 14.3 Clocking block declaration
- A clockvar whose clocking_direction is inout shall behave as if it were two clockvars, one input and one output, having the same name and the same clocking_signal.
- Reading the value of such an inout clockvar shall be equivalent to reading the corresponding input clockvar.
- Writing to such an inout clockvar shall be equivalent to writing to the corresponding output clockvar.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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