Wire vs. Logic in SV Interface

SystemVerilog
, ,
5

In reply to MayurKubavat:

Here is a small example which demonstrates an interface that can be used as a master/slave:


interface intf(input clock);
  wire a;
  wire b;

  bit mode = 1;   // 1 - Master ; 0 - Slave - You can use an enum
 
  logic a_i;
  logic b_1;

  assign a = (mode==1) ? a_i : 1'bz;
  assign b = (mode==1) ? b_i : 1'bz;

  function void set_mode(bit new_mode)
    mode = new_mode;
  endfunction
...

You can read all of the inputs using the wires. You can use the logic variables in your procedural code, which you can’t do with wires. This solution also eliminates the multiple driver warnings/errors.